Design and Implementation of Three Dimensional Arithmetic Units

We describe the design and the implementation of two three dimensional arithmetic units: a 3D adder and a 3D multiplier. Compared to their 2D counterparts, our 3D adder incurs 10.6–34.3% less delay and 11.0–46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory.